DMR Slot 2, overflow in the DMR slot RF queue

Help with DMR issues
KB0FX
Posts: 2
Joined: Fri Feb 18, 2022 1:47 am

DMR Slot 2, overflow in the DMR slot RF queue

Post by KB0FX »

I am seeing DMR Slot 2, overflow in the DMR slot RF queue messages appearing over and over again in Live Logs for the DMR repeater for which I am the SysOp. This appears to only occur on certain stations that are connecting through a HotSpot. Those stations also show Loss on the Pi-Star Dashboard for the repeater. I have included the log below. Running Version 4.1.6 of Pi-Star. any idea what is causing this?

73 - Mike - KB0FX

M: 2022-02-28 18:20:46.796 DMR Slot 2, received RF end of voice transmission from KB0FX to TG 31292, 9.1 seconds, BER: 1.0%, RSSI: -133/-130/-131 dBm
M: 2022-02-28 18:20:51.592 DMR Slot 2, received network voice header from KA0DAY to TG 31292
M: 2022-02-28 18:20:51.706 DMR Talker Alias (Data Format 3, Received 3/13 char): 'KA0'
M: 2022-02-28 18:20:51.706 DMR Slot 2, Embedded Talker Alias Header
M: 2022-02-28 18:20:51.706 0000: 04 00 DA 00 4B 00 41 00 30 *....K.A.0*
M: 2022-02-28 18:20:52.413 DMR Talker Alias (Data Format 3, Received 6/13 char): 'KA0DAY'
M: 2022-02-28 18:20:52.413 DMR Slot 2, Embedded Talker Alias Block 1
M: 2022-02-28 18:20:52.413 0000: 05 00 00 44 00 41 00 59 00 *...D.A.Y.*
M: 2022-02-28 18:20:53.138 DMR Talker Alias (Data Format 3, Received 10/13 char): 'KA0DAY DMR'
M: 2022-02-28 18:20:53.138 DMR Slot 2, Embedded Talker Alias Block 2
M: 2022-02-28 18:20:53.138 0000: 06 00 20 00 44 00 4D 00 52 *.. .D.M.R*
M: 2022-02-28 18:20:53.806 DMR Talker Alias (Data Format 3, Received 13/13 char): 'KA0DAY DMR ID'
M: 2022-02-28 18:20:53.806 DMR Slot 2, Embedded Talker Alias Block 3
M: 2022-02-28 18:20:53.806 0000: 07 00 00 20 00 49 00 44 00 *... .I.D.*
E: 2022-02-28 18:21:55.308 DMR Slot 2, overflow in the DMR slot RF queue
E: 2022-02-28 18:21:56.316 DMR Slot 2, overflow in the DMR slot RF queue
E: 2022-02-28 18:21:56.316 DMR Slot 2, overflow in the DMR slot RF queue

DELETED LOG SECTION......

E: 2022-02-28 18:22:46.260 DMR Slot 2, overflow in the DMR slot RF queue
E: 2022-02-28 18:22:46.260 DMR Slot 2, overflow in the DMR slot RF queue
M: 2022-02-28 18:22:46.260 DMR Slot 2, received network end of voice transmission from KA0DAY to TG 31292, 130.8 seconds, 13% packet loss, BER: 0.0%
M: 2022-02-28 18:23:03.771 Downlink Activate received from KB0FX
VA2KPJ
Posts: 1
Joined: Tue Jan 03, 2023 7:29 pm

Re: DMR Slot 2, overflow in the DMR slot RF queue

Post by VA2KPJ »

i've got the same problem and still looking answers
KN2TOD
Posts: 262
Joined: Sun Nov 11, 2018 6:36 pm

Re: DMR Slot 2, overflow in the DMR slot RF queue

Post by KN2TOD »

Been seeing this phenom for months now. It does seem to be getting more prevalent as well.

My first encounter with this problem came when one of hotspots froze up because the log directory hit 100%. Had to write a quick script to cull the logs down to get things back on track.

Some observations, FWIW, over the last several months:
  • 1. seems to be external to the hotspots, i.e. the overflows are not being generated by the hotspots and dumped out to the servers (basing this on the fact that I have little if any outbound traffic but once or twice a week, but am seeing the overflows virtually every day.)

    2. looking for possible RFI contributing to the problem, can neither correlate that with known sources or get it to trigger from a known source.

    3. does seem to occur on heavily used TG's like 91 and 31656, but occasionally on other lesser used TG's.

    4. occurs on both simplex and duplex setups; on either time slot.

    5. does not seem to matter which BM repeater is being used.

    6. seems to occur either right after the transmission starts or near the end of a transmission; sometimes the transmission dies - no "end of voice" is received,; occasional watchdog timeout messages related to the QSO is seen.

    7. adjusting the MTU values for the inet traffic does not appear to effect the problem (on the off chance there was/is packet fragmentation).
It's a mystery; can't find much about it on net either.

Speculations:
  • 1. someone is experimenting with new versions of MMDVM host or firmware code?

    2. something like APRS traffic is messing things up?

    3. protocols between various digital modes/gateways are messed up (technical term)?
Any one have anything to add to this, anything to look at further, I'm all ears. Seems like we need a collective investigation to get to the bottom on this.
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G8SEZ
Posts: 553
Joined: Fri Apr 13, 2018 8:26 pm

Re: DMR Slot 2, overflow in the DMR slot RF queue

Post by G8SEZ »

Check that the modem firmware is up to date.
--

Brian G8SEZ
KN2TOD
Posts: 262
Joined: Sun Nov 11, 2018 6:36 pm

Re: DMR Slot 2, overflow in the DMR slot RF queue

Post by KN2TOD »

All applicable firmware is up-to-date here. Yet, others may be modifying (and testing) theirs. Who knows?
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G8SEZ
Posts: 553
Joined: Fri Apr 13, 2018 8:26 pm

Re: DMR Slot 2, overflow in the DMR slot RF queue

Post by G8SEZ »

I have seen this error on occasion in the past, I never did quite get to the bottom of why.

I suppose all you can do is grep the source for the string and work out what triggers it, I am fairly sure it's to do with the connection between the modem and the hardware running the MMDVM host process.

Other than that, I don't have any better ideas.

G4KLX might know more.
--

Brian G8SEZ
K3SZ
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Joined: Tue May 07, 2019 6:50 pm

Re: DMR Slot 2, overflow in the DMR slot RF queue

Post by K3SZ »

I'm rarely on this forum but ran across this post. I've seen this problem before myself and had similar entries in my live log. I had found that the ADF7021, pin 39, was not getting a good clock signal. The TCXO's output looked fine on the oscilloscope but was distorted on the other side of the coupling capacitor that connects the clock signal to the ADF7021. A second board showed no clock at all -- just a positive DC offset with some noise on it.

This occurred with two different N5BOC simplex boards. The first two exhibited this problem but the third one worked fine. I exchanged a lot of emails with N5BOC but I never did find out what the exact cause was. Don't know if the cap was defective, a cold solder joint, or some other issue.
KN2TOD
Posts: 262
Joined: Sun Nov 11, 2018 6:36 pm

Re: DMR Slot 2, overflow in the DMR slot RF queue

Post by KN2TOD »

Been monitoring this problem for a couple months now and from time to time would get the sense noise/interference was the culprit but could never pin it down or correlate it to or even reproduce it with the any of the usual environmental sources. A drifting clock was another thought I had. But what you say makes sense.

I have a couple N5BOC boards but I'm seeing it on some zumspot boards as well, which would suggest a circuit design problem perhaps? Tolerances too close for comfort?

I can see occasional clocking blips as natural but sometimes these overflows run for several seconds and a tight grouping, which leads me to think that this may be voltage related?

Since you're working at the "pin" level here, is low-voltage a situation you can test? To see if it can be reproduced?

Thanks for your input!
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G8SEZ
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Joined: Fri Apr 13, 2018 8:26 pm

Re: DMR Slot 2, overflow in the DMR slot RF queue

Post by G8SEZ »

I recall the ADF7021 issue with the clock coupling capacitor and the question of whether it is necessary. If you have a square wave output TCXO it is not needed, it's only if there is a sine wave output which needs AC coupling to avoid upsetting the bias on the clock input, I don't know if there is a register setting for this as some devices do change the bias setup.

Food for thought.
--

Brian G8SEZ
KN2TOD
Posts: 262
Joined: Sun Nov 11, 2018 6:36 pm

Re: DMR Slot 2, overflow in the DMR slot RF queue

Post by KN2TOD »

[My days of working at the circuit level are long gone so I appreciate your insights here.]

Do we know for sure that the errant clocking causes the message to be generated? Is there a way to have the firmware "defense" against this, i.e. to detect the bad clocking and/or the erroneous data that results from it? (I know, I know: the logic is dependent on the clock to execute the code to determine if the clock is bad .... but I thought I ask anyway. :P )
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